|Table of Contents|

Analysis of Multiple-line Redundant Circuits

《南京理工大学学报》(自然科学版)[ISSN:1005-9830/CN:32-1397/N]

Issue:
2005年01期
Page:
40-42
Research Field:
Publishing date:

Info

Title:
Analysis of Multiple-line Redundant Circuits
Author(s):
JIANG Li-ping TAN Xue-qin
School of Electronic Engineering and Photoelectronic Technology, NUST, Nanjing 210094,China
Keywords:
comb inational circuits mu ltiple-line redundancy fault detection
PACS:
TN702
DOI:
-
Abstract:
The redundancy caused by incorrect c ircu it design causes the increase o f c ircu it cos.t A lso, it makes fault detect ion of netwo rk diff icu lt or impossib le. The know ledge onmultiple-line redundancy is introduced. Then, ame thod to create arbitrarymultiple-line redundant c ircuit is proposed. The created c ircu it has one characterist ic, that is, the circu it itself ismu ltiple-line redundancy but its subnet is irredundan. t Any f ixed leve l fault wh ich is less than k-tuple is detectable

References:

[ 1] Ne lson V P, T roy N ag le H, Carro ll B D, e t a.l D ig ita l log ic c ircu it ana lys is and design [M ]. [ S. L. ] : Prentice- H all Interna tiona ,l Inc 1995.
[ 2] Cheng K T, Entrena L A. Mu lt-i level log ic optim iza tion by redundancy add ition and remova l [ A] . European Confe rence on Design Autom ation [ C ]. [ S. L. ]: EDAC-93 IEEE, 1993: 373- 377.
[ 3] 周南良. 数字逻辑[M ]. 长沙: 国防科技大学出版社, 1993.

Memo

Memo:
-
Last Update: 2013-03-03